Mbedded Logic
Register here for Mbedded Logic. Last date of registration is 20th December 2009.
Accommodation Application Form is available. Last Date for Abstract Submission for Accommodation is 25th December 2009.
For all the Updates and Discussion please visit the Techfest Forum.
FPGA - the Field Programmable Gate Arrays - are a buzzword of today. One of the ingenuities of mankind, FPGAs have indeed revolutionized the way electronic designs are made, tested and implemented. Coupled with the low power dissipation and the ability to let the user erase and re-load the new code on-field, FPGAs are the ideal tool in the hands of electronics engineers. No wonder the really fast moving FMCG companies in the field of electronics use this boon to the fullest.
Techfest 2010 provides you a hands-on with Mbedded Logic.
1.1 Problem Statement
Implement the miniMIPS structure for simple instructions using FPGA.
Register here for Mbedded Logic. Prizes worth INR 16,000 to be won.
For answers to your queries/doubts, register on our Forum.
View the Specifications »
For further queries contact:
|
Harshad Patil |
Nishank Gupta |
2.1 Specifications
- a. Hardware description
The miniMIPS is a 32-bit microprocessor with a reduced instruction set architecture (RISC). This implementation should have the MIPS word-addressable, i.e. currentPC + 1 addresses the next word and not the next byte. There are five stages for the completion of an instruction - instruction fetch, instruction decode, execution, memory read/write and writeback - therefore the pipeline is 5 stages deep. The architecture is shown as below:
Single cycle MIPS Glossary:
- PC - Program Counter - Generates the next address and sends it to the instruction cache.
- Instruction Cache - This is 128 words wide. The microprocessor instructions are stored in this block. The cache is word addressable.
- Register Bank - Contains 32 registers. R0 cannot be modified and stores zero always (zero register). R31 is used as the system register and stores the PC for the jump and link (jal) instruction
- ALU - Arithmetic and Logic Unit.
- Data Cache - 128 words wide. Acts as memory. Data cache is also word addressable.
Multicycle MIPS - b. Instructions
Here rd, rs and rt are registers. 5 bits are needed to address 32 registers. The immediate is always 16 bits wide.
- c. Instruction Set
- Add: add rd, rs, rt ------- rd = rs + rt
- Add immediate: addi rd, rs, imm ------ rd = rs + (extended) imm
- Subtract: sub rd, rs, rt ---------- rd = rs - rt
- Set less than: slt rd, rs, rt ----------- if (rs < rt) rd = 0 else rd = 1
- Set less than zero: sltz rd, rs ------------- if (rs < 0) rd = 0 else rd = 1
- Load upper immediate: lui rd, imm ---------- load immediate into the upper half of rd. The lower half is zero
- AND: and rd, rs, rt --------- rd = rs && rt (bitwise and)
- OR: or rd, rs, rt ----------- rd = rs || rt (bitwise or)
- ANDi - and immediate: andi rd, rs, imm ------ rd = rs && (extended) imm
- ORi - or immediate: ori rd, rs, imm ------- rd = rs || (extended) imm
- NOR: nor rd, rs, rt ---------- rd = bitwise nor (rs, rt)
- XOR: xor rd, rs, rt ---------- rd = bitwise xor (rs, rt)
- Load word: lw rd, rs, imm ------- rd = data stored at memory address (rs + imm ) in data cache
- Store word: sw rd, rs, imm ------- store the data in rd at the memory address (rs + imm) in data cache
- Jump: j imm ----------------- jump to the instuction PC + imm ie. Next PC = PC + imm
- Jump Register: jra rd -------------------jump to the address located in rd ie. Next PC = $rd
- Branch Less than zero: bltz rd, imm ----------- if (rd < 0) go to PC + imm ie. Next PC = PC + imm
- Branch equal: be rd, rs, imm --------- if (rd == rs) go to PC + imm ie. Next PC = PC + imm
- Branch not equal: bne rd, rs, imm --------- if (rd != rs) go to PC + imm ie. Next PC = PC + imm
- Jump and link: jal, imm ------------------ jump to the address PC + imm and store the next PC (ie. PC + 1) in r31.
- NOP: nop ------------------------ no operation
d. Pipelined Implementation
Each instruction has 5 stages.
instruction fetch, instruction design, execution, memory access and write back
| IF | ID | EX | MA | WB |
| IF | ID | EX | MA | WB |
After the first instruction is fetched, the next instruction is fetched without waiting for the first instruction to complete.
As the instruction propagates through the pipeline, it must carry information and data regarding its execution to the subsequent stages (eg, carrying the data and memory address and read / write signals from the decode stage to the memory access stage.) This data is stored in special registers.e. Data Forwarding:
In the pipelined implementation, each instruction takes at most 5 cycles to complete. However this can give rise to data conflicts.Ex. lui r2, 0040H
lui r1, 0020H
add r3, r2, r1
instr 1 | IF | ID | EX | MA | WB |
instr 2 | IF | ID | EX | MA | WB |
instr 3 | IF | ID | EX | MA | WB |
cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
the data for r2 is available at the end of the cycle 3 while data for r1 is availabe at the end of cycle 4. Instead of waiting
for both the data to be written back into the memory, we can "forward" the data directly to the execution stage of the 3rd
instruction. As a result on can increase the throughput of the processor and waste fewer cycles.
View the General Rules »
3.1 General Rules
- The platform for implementation is the FPGA kit: XC3S500E.
- Coding can be done in either VHDL or Verilog.
- Do not forget to insert comments in the code at proper places for better understanding of the same.
- We have provided the software links for Xilinx and ModelSim for your help. These softwares are needed to be used in the competition.View Resources
- You need to create a separate Test-bench yourselves for testing the code.
- You have to submit the code along with the Test-bench on the event day. The latest results should also be brought in for verification.
- The code will be tested on the FPGA in the organizers' electronics laboratory.
View the Rules »
3.2 Abstract submission
- The participant teams need to submit an abstract to get shortlisted for the final round.
- The abstract should be sent as a zip folder to mbeddedlogic[at]techfest.org .
- The zip folder should have the following contents:
- All the folders containing well commented synthesizable code for the miniMIPS structure.
- A Readme.txt file explaining the heirarchy and contents of folders and also contents of the file in brief.
- The zip file should be named MLXXXX.zip where "XXXX" is your registration number.
- The last date for submission of abstract for accommodation is 25th of December, 2009 2355 hrs.
- The last date for submission for teams not requiring accommodation is 31st of December, 2009 2355 hrs
4.1 Team Specifications
A team can have a maximum of 2 members. Students from different educational institutions can form a team.
4.2 Eligibility
Any student of any institute, who has a valid Identity Card of his institute for the year 2009-10 is allowed to participate.
4.3 Judging Criterion
Objective criterion: Maximum frequency of operation and minimum power dissipation will fetch higher credit.
Subjective criterion: The superiority of the code and the team's performance in the viva conducted by the judges will be the two criteria here.
Elimination criterion:Code has to be synthesizeable, data forwarding is not mandatory for elimination..
Judges' decision will be final and binding on all.
4.4 Certificate Policy
- Certificate of Excellence will be given to all the winners.
- Certificates of Participation will be given to all the teams who will qualify the elimination.
Register here for Mbedded Logic.
5.1 Software
ModelSim Student Edition
Linux Edition
Windows Edition
Installation Notes
Xilinx software
ISE Webpack
5.2 Computer Architecture
5.3 VHDL Tutorials
- http://en.wikipedia.org/wiki/VHDL
- http://www.vhdl-online.de/tutorial/
- http://www.doulos.com/knowhow/vhdl_designers_guide/
- http://www.gmvhdl.com/VHDL.html
- http://www.ashenden.com.au/designers-guide/VHDL-quick-start.pdf
- http://www.angelfire.com/in/rajesh52/verilogvhdl.html
- http://esd.cs.ucr.edu/labs/tutorial/
5.4 Reference Books
- Behrooz Parhami , Computer Architecture.
- Ewa Z. Bem and Luke Petelczyc - “MiniMIPS – a Simulation Project for the Computer Architecture Laboratory ”
